Proof that akers’ algorithm for locally exhaustive testing gives minimum test sets of combinational circuits with up to four outputs

نویسندگان

  • Hiroyuki Michinishi
  • Tokumi Yokohira
  • Takuji Okamoto
چکیده

In this paper, we prove that Akers' test generation algorithm for the locally exhaustive testing gives a minimum test set (MLTS) for every combinational circuit (CUT) with up to four outputs. That is, we clanfi that Akers' test pattern generator can generate an MLTS for such CUT.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Test Pattern Generation and Test Application Time

As the complexity of VLSI circuits is increasing at the rate predicted by Moore's law and the switching frequencies are approaching a gigahertz, testing cost is becoming an important factor in the overall IC manufacturing cost. Testing cost is incurred by test pattern generation and test application processes. In this dissertation, we address both of these factors contributing to the testing co...

متن کامل

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets

The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. The test data outputs in BIST are ultimately compressed by the time compaction hardware, commonly called a response analyzer, into signatures. Several output response compaction techniques to aid in the synthesis of such support circui...

متن کامل

Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

متن کامل

A timing-driven pseudoexhaustive testing for VLSI circuits

Because of its ability to detect all non-redundant combinational faults, exhaustive testing, which applies all possible input combinations to a circuit, has become a very attractive test method. However, the test application time for exhaustive testing can be very large. To reduce the test time, pseudo exhaustive testing inserts some bypass storage cells (bscs) so that the dependency of each no...

متن کامل

On IDDQ Measurement Based Analysis of Bridging Faults in CMOS Circuits1

An algorithmic paradigm for I DDQ measurement based analysis that target all two node bridging faults (BFs) in CMOS circuits is presented. In contrast to the pessimistic criteria used in our prior work, here we use the criteria for identifying I DDQ tests proposed in the literature by other researchers. Algorithms for simulation, diagnosis and I DDQ subset selection of BFs in combinational circ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2010